Superconducting latching/SFQ hybrid RAM

被引：7

作者：

Nagasawa, S ^{[1
]}

Hasegawa, H ^{[1
]}

Hashimoto, T ^{[1
]}

Suzuki, H ^{[1
]}

Miyahara, K ^{[1
]}

Enomoto, Y ^{[1
]}

机构：

[1] ISTEC, Superconduct Res Lab, Inzai 2701382, Japan

来源：

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 2001年 / 11卷 / 01期

关键词：

Josephson junction; random access memory; single flux quantum device; latching device;

D O I：

10.1109/77.919400

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a 256-bit superconducting latching/SFQ hybrid (SLASH) RAM block as the first step in developing a 16-Kbit SLASH RAM, which enables high-frequency clock operation up to 10 GHz The SLASH RAM is composed of ac-powered latching devices and de-powered SFQ devices. The 256-bit SLASH RAM block is composed of 16x16 matrix array of vortex transitional memory cells, SFQ-NOR decoders, latching drivers, latching sense circuits, and address buffers. The 256-bit SLASH RAM block chips were fabricated and tested. We confirmed that the 256-bit SLASH RAM block functioned successfully.

引用

页码：533 / 536

页数：4

共 8 条

[1]

HERR QP, 1999, ISEC 99, P362

[2]

Kirichenko A. F., 1999, ISEC 99, P124

[3] A 380 PS, 9.5 MW JOSEPHSON 4-KBIT RAM OPERATED AT A HIGH BIT YIELD [J].