Quotient-selected modified signed-digit division algorithm and its optoelectronic implementations

A novel optoelectronic quotient-selected modified signed-digit division technique is proposed This division method generates one quotient digit per iteration involving only one shift operation, one quotient selection operation and one addition/subtraction operation. The quotient digit can be selected by observing three most significant digits of the partial remainder independent of the divisor. Two algorithms based on truth-table look-up and binary logic operations have been derived. For optoelectronic implementation, an efficient shared content-addressable memory based architecture as well as compact logic array processor based architecture with an electron-trapping device is proposed. Performance evaluation of the proposed optoelectronic quotient-selected division shows that it is faster than the previously reported convergence division approach. Finally, proof-of-principle experimental results are presented to verify the effectiveness of the proposed technique.