Rapid Prototyping of an Automated Video Surveillance System: A Hardware-Software Co-Design Approach

被引:0
作者
Ngo, Hau T. [1 ]
Rakvic, Ryan N. [1 ]
Broussard, Randy P. [2 ]
Ives, Robert W. [1 ]
机构
[1] US Naval Acad, Dept Elect & Comp Engn, Annapolis, MD 21402 USA
[2] US Naval Acad, Weapons & Syst Engn Dept, Annapolis, MD 21402 USA
来源
MOBILE MULTIMEDIA/IMAGE PROCESSING, SECURITY, AND APPLICATIONS 2011 | 2011年 / 8063卷
关键词
FPGA; real-time image processing; embedded system; Nios-II processor; pipeline and systolic architecture; foreground segmentation;
D O I
10.1117/12.884331
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
FPGA devices with embedded DSP and memory blocks, and high-speed interfaces are ideal for real-time video processing applications. In this work, a hardware-software co-design approach is proposed to effectively utilize FPGA features for a prototype of an automated video surveillance system. Time-critical steps of the video surveillance algorithm are designed and implemented in the FPGA's logic elements to maximize parallel processing. Other non time-critical tasks are achieved by executing a high level language program on an embedded Nios-II processor. Pre-tested and verified video and interface functions from a standard video framework are utilized to significantly reduce development and verification time. Custom and parallel processing modules are integrated into the video processing chain by Altera's Avalon Streaming video protocol. Other data control interfaces are achieved by connecting hardware controllers to a Nios-II processor using Altera's Avalon Memory Mapped protocol.
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页数:9
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