An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

被引：8

作者：

Saini, Sandeep ^{[1
]}

Kumar, A. Mahesh ^{[1
]}

Veeramachaneni, Sreehari ^{[1
]}

Srinivas, M. B. ^{[2
]}

机构：

[1] Int Inst Informat Technol Hyderabad, Ctr VLSI & Embedded Syst Technol, Hyderabad 500032, Andhra Pradesh, India

[2] Birla Inst Technol & Sci, Elect & Commun Engn, Hyderabad 500078, Andhra Pradesh, India

来源：

23RD INTERNATIONAL CONFERENCE ON VLSI DESIGN | 2010年

关键词：

OPTIMIZATION;

D O I：

10.1109/VLSI.Design.2010.53

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In VLSI interconnect buffers are used to restore the signal level affected by the parasitics However buffers have a certain switching time that contributes to overall signal delay Further the transitions that occur in Interconnects also contribute to crosstalk delay Thus the overall delay in interconnects is due to combined effect of both buffer and crosstalk delay In this work a replacement of buffers with Schmitt trigger is proposed for the same purpose of signal restoration Due to lower threshold voltage of Schmitt trigger signal can rise early and the large noise margin of schmitt trigger helps in reducing the noise glitches as well Simulation results shows that thethe Schmitt trigger approach gives 20% delay reduction as compared to 10 4% in case of buffers

引用

页码：411 / +

页数：3

共 11 条

[1]

Alpert C, 1997, DES AUT CON, P588, DOI 10.1145/266021.266291

[2]

Alpert CJ, 2002, IEEE T COMPUT AID D, V21, P3

[3] Steiner tree optimization for buffers, blockages, and bays [J].