Low Voltage Complementary Metal Oxide Semiconductor Based Energy Efficient UART Design on Spartan-6 FPGA

被引：1

作者：

Kumar, Abhishek ^{[1
]}

Pandey, Bishwajeet ^{[2
]}

Hussain, D. M. Akbar ^{[3
]}

Rahman, Mohammad Atiqur ^{[4
]}

Jain, Vishal ^{[5
]}

Bahanasse, Ayoub ^{[6
]}

机构：

[1] Gyanc Res Consultancy, Res & Dev Wing, Motihari, India

[2] Gyanc Res Lab, Ctr Energy Excellence, Motihari, India

[3] Aalborg Univ, Dept Energy Technol, Esbjerg, Denmark

[4] SYNERGY, Res & Dev Sect, Dhaka, Bangladesh

[5] Bharati Vidyapeeth, Dept Comp Applicat, New Delhi, India

[6] Hasan II Univ, Lab LTI, Casablanca, Morocco

来源：

2019 11TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS (CICN 2019) | 2019年

关键词：

FPGA; UART; LVCMOS; Energy efficient; High Speed;

D O I：

10.1109/CICN.2019.16

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

UART is the most popular two-wire communication interface. It is recognized as Universal Asynchronous Receiver Transmitter. It is a one of the essential element in Communication System to communicate two micro controller based system. It is widely used in case of small distance communication. The implementation of UART's with VHDL can be unified into FPGA for the achievement of stable, reliable, and compact data transmission. Our main aim to implement and design an energy efficient model for that we have used the LVCMOS IO standards and we are comparing our design with a normal UART. In this paper, it has been illustrated that the demand for total power reduced with LVCMOS IO/Standard based UARTs in compare to default IO standards. This paper illustrates differences on the basis of the power consumption by the LVCMOS based energy efficient Universal Asynchronous Receiver Transmitter (UART) and Default IO/Standard based UARTs.

引用

页码：84 / 87

页数：4

共 6 条

[1]

Isha Gupta Garima, 2015, INDIAN J SCI TECHNOL, V8, P1

[2]

Kaur H., 2016, 6 INT C COMM NETW TE

[3]

Kumar T., 2013, INT C GREEN COMP COM, P1

[4]

More J., ONL INT C GREEN ENG

[5] Input-Output Standard-Based Energy Efficient UART Design on 90 nm FPGA [J].

Sharma, Rashmi ;

Pandey, Bishwajeet ;

Jha, Vikas ;

Saurabh, Siddharth ;

Dabas, Sweety .

SYSTEM AND ARCHITECTURE, CSI 2015, 2018, 732 :139-150

[6] Thermal Aware Low Power Universal Asynchronous Receiver Transmitter Design on FPGA [J].

Singh, Sunny ;

Jain, Abhishek ;

Kaur, Amanpreet ;

Pandey, Bishwajeet .

2014 6TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS, 2014, :940-943

← 1 →