Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown

被引:18
作者
Bashir, Muhammad [1 ]
Milor, Linda [1 ]
Kim, Dae Hyun [1 ]
Lim, Sung Kyu [1 ]
机构
[1] Georgia Tech, Sch ECE, Atlanta, GA 30332 USA
基金
美国国家科学基金会;
关键词
D O I
10.1016/j.microrel.2010.07.091
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low-k time-dependent dielectric breakdown (TDDB) has been found to be a function of metal linewidth, when the distance between the lines is constant. Modeling requires determining the relationship between TDDB and layout geometries. To determine this relationship, comb test structures have been design and implemented in 45 nm technology. In this work, low-k dielectric breakdown, low-k dielectric vulnerable areas, and linewidth variation are linked to full chip lifetimes. (C) 2010 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1341 / 1346
页数:6
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