Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

被引:8
作者
Yao, Jia-Fei [1 ,2 ]
Guo, Yu-Feng [1 ,2 ]
Zhang, Zhen-Yu [1 ,2 ]
Yang, Ke-Meng [1 ,2 ]
Zhang, Mao-Lin [1 ,2 ]
Xia, Tian [3 ]
机构
[1] Nanjing Univ Posts & Telecommun, Coll Elect & Opt Engn Coll Microelect, Nanjing 210023, Peoples R China
[2] Natl & Local Joint Engn Lab RF Integrat & Microas, Nanjing 210023, Peoples R China
[3] Univ Vermont, Sch Elect Engn, Burlington, VT 05405 USA
基金
中国国家自然科学基金;
关键词
high-k dielectric; step doped silicon pillar; model; breakdown voltage; ANALYTICAL-MODEL; MOSFET;
D O I
10.1088/1674-1056/ab6960
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (R-on,R- sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R-on,R- sp compared to the SD device and HK device.
引用
收藏
页数:8
相关论文
共 21 条
[1]  
Baliga B. J., 2010, Fundamentals of Power Semiconductor DevicesJ
[2]   MOSFET transistors fabricated with high permitivity TiO2 dielectrics [J].
Campbell, SA ;
Gilmer, DC ;
Wang, XC ;
Hsieh, MT ;
Kim, HS ;
Gladfelter, WL ;
Yan, JH .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (01) :104-109
[3]  
Chen WJ, 2007, INT C COMMUN CIRCUIT, P1256
[4]   Optimization of super-junction SOI-LDMOS with a step doping surface-implanted layer [J].
Chen, Wanjun ;
Zhang, Bo ;
Li, Zhaoji .
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2007, 22 (05) :464-470
[5]   A Vertical Power MOSFET With an Interdigitated Drift Region Using High-k Insulator [J].
Chen, Xingbi ;
Huang, Mingmin .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (09) :2430-2437
[6]   New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping [J].
Duan, Baoxing ;
Cao, Zhen ;
Yuan, Xaoning ;
Yuan, Song ;
Yang, Yintang .
IEEE ELECTRON DEVICE LETTERS, 2015, 36 (01) :47-49
[7]  
FAN J, 2018, CHINESE PHYS LETT, V35
[8]  
Guo Y F, 2006, IEEE INT C COMM CIRC
[9]   A new analytical model for optimizing SOI LDMOS with step doped drift region [J].
Guo, Yufeng ;
Li, Zhaoji ;
Zhang, Bo .
MICROELECTRONICS JOURNAL, 2006, 37 (09) :861-866
[10]   A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology [J].
Hu, Yue ;
Wang, Hao ;
Du, Caixia ;
Ma, Miaomiao ;
Chan, Mansun ;
He, Jin ;
Wang, Gaofeng .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (05) :1969-1976