3D stacking using bump-less process for sub 10um pitch interconnects

被引：21

作者：

Derakhshandeh, Jaber ^{[1
]}

De Preter, Inge ^{[1
]}

Gerets, Carine ^{[1
]}

Hou, Lin ^{[1
]}

Heylen, Nancy ^{[1
]}

Beyne, Eric ^{[1
]}

Beyer, Gerald ^{[1
]}

Slabbekoorn, John ^{[1
]}

Dubey, Vikas ^{[1
]}

Jourdain, Anne ^{[1
]}

Potoms, Goedele ^{[1
]}

Inoue, Fumihiro ^{[1
]}

Jamieson, Geraldine ^{[1
]}

Vandersmissen, Kevin ^{[1
]}

Suhard, Samuel ^{[1
]}

Webers, Tomas ^{[1
]}

Capuz, Giovanni ^{[1
]}

Wang, Teng ^{[1
]}

Rebibis, Kenneth June ^{[1
]}

Miller, Andy ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium

来源：

2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2016年

关键词：

D O I：

10.1109/ECTC.2016.377

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.

引用

页码：128 / 133

页数：6