A 1.1 G MAC/s sub-word-parallel digital signal process of for wireless communication applications

被引：5

作者：

Huang, YH ^{[1
]}

Ma, HP

Liou, ML

Chiueh, TD

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

[2] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[3] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 01期

关键词：

digital signal processor (DSP); sub-word parallelism; wireless communication;

D O I：

10.1109/JSSC.2003.820861

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication Systems. The OFDM-based IEEE, 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are. simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The. processor chip is. fabricated using a 0.35-mum n-well one-poly four-metal MOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.

引用

页码：169 / 183

页数：15

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