Active Learning Framework for Post-Silicon Variation Extraction and Test Cost Reduction

Traditional process variation modeling is primarily focused on design-time analysis and optimization. However, with the advances of post-silicon techniques, accurate variation model is also highly desired in various post-silicon applications, such as post-silicon tuning, test vector generation, and reliability prediction. The accuracy of such post-silicon variation models is greatly improved by incorporating test measurements from each wafer or die. However, to limit test cost, the number of measurements must be reduced as much as possible. This paper proposes an active learning framework to dynamically extract post-silicon process variation models with tightened variance from measurements. The framework is composed of two stages, active training and model adaptation. Active training collects information and initializes the models to be used for the forthcoming wafers. Model adaptation stage then validates the models and optimally determines the test configuration for partial testing to reduce the test cost. Experimental results based on the measurements from two industrial processes show that the proposed framework can achieve variation models with variance reduction of similar to 80% when compared with design-time variation models. Meanwhile, the average estimation error for those untested sites is well maintained at similar to 2-3% using merely similar to 30% available test structures for two processes.