Time-to-Digital Converter With Sample-and-Hold and Quantization Noise Scrambling Using Harmonics in Ring Oscillators

被引：12

作者：

Caram, Juan Pablo ^{[1
,2
]}

Galloway, Jeff ^{[2
]}

Kenney, J. Stevenson ^{[1
]}

机构：

[1] Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA

[2] Silicon Creat LLC, Suwanee, GA 30024 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2018年 / 65卷 / 01期

关键词：

Time-to-digital converter; digital phase-locked loop; sample-and-hold; oversampling; ring oscillator; harmonics; PHASE NOISE; CMOS; JITTER; ERRORS; TDC;

D O I：

10.1109/TCSI.2017.2712518

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-resolution, high-bandwidth, and noise-scrambling, time-to-digital converter (TDC) is presented. Its architecture, which exploits harmonics in ring oscillators, provides a sample-and-hold mechanism in the form of relative phase. This storage mechanism is highly insensitive to noise and allows for oversampling between input events, therefore, can be designed for very high bandwidth. It can achieve lower quantization noise with fewer measurements than noise-shaping TDCs. This paper presents the architecture in detail, an in-depth analysis of noise sensitivity of the time storage mechanism, and the results from a prototype implemented in a 28-nm CMOS process.

引用

页码：74 / 83

页数：10

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