A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

被引：12

作者：

Sundstrom, Timmy ^{[1
]}

Svensson, Christer ^{[1
]}

Alvandpour, Atila ^{[1
]}

机构：

[1] Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2011年 / 46卷 / 07期

关键词：

Analog-to-digital converter (ADC); CMOS analog integrated circuits; current-mode; data converter; foreground digital calibration; high speed; low power; pipeline;

D O I：

10.1109/JSSC.2011.2143811

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample rate is achieved through the use of fast open-loop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65 nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.

引用

页码：1575 / 1584

页数：10

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