Optimization of thermal resistance in quasi monolithic integration technology (QMIT) structure

Static thermal analysis of the standard structure of QMIT has already been performed and effect of different factors and parameters such as thermal conductivity of epoxy, distance between active device and Si substrate (W), front side substrate metallization and heat spreader on the back side have been described [1-2]. In the first structure (or standard structure) of QMIT (Fig. 1(a)) the holes in which the active devices are placed have been created by using conventional wet etching of silicon in KOH. It is well known that by using dry etching, the holes dimensions on the front side of Si-wafer are more uniform, accurate and reproducible. There are two other possible structures, one by using the full dry etching (Fig. 1(b)) and through a combination of wet etching and dry etching (Fig. 1(c)). In this paper a 2D finite element (FE) static heat transfer simulation has been used to find the best structure among these three structures and optimise its geometry and all its physical properties to have a lower thermal resistance which makes it possible to use QMIT for high power microwave circuit applications. The results show that a combination of dry etching and wet etching gives a lower thermal resistance than the other two and with backside plating of 275 mum gold as a heat spreader, epoxy thermal conductivity of 4 W/m.K and W of 5 mum, a thermal resistance of less than 10 degreesC/W is possible.