Design and implementation of a pipelined 8 bit-serial single-flux-quantum microprocessor with cache memories

A pipelined 8 bit- serial single- flux- quantum microprocessor integrating cache memories, called CORE1 gamma, has been designed and implemented. The CORE1 gamma has 16 byte and 8 byte shift- register- based cache memories for instructions and for data, respectively. The microprocessor overlaps four instructions in pipeline executions. The pipeline stages are optimized to control the cache memories and a new circuit component is developed to manage the pipeline execution according to whether each cache hits or misses. Advanced passive transmission line techniques with use of the cell library of the 2.5 kA cm(-2) niobium standard process are utilized to implement the CORE1 gamma accompanied by extremely complex interconnects. The CORE1 gamma is made up of 295 passive interconnects, and 22302 Josephson junctions are integrated on a 6.36 x 6.36 mm(2) area. The logic simulation shows that the peak performance is estimated at 1000 million operations per second, and it is kept even during memory access as long as the cache memories hit.