A Fault Prediction Module for a Fault Tolerant NoC Operation

被引:0
作者
Silveira, Jarbas [1 ]
Bodin, Mathieu [2 ]
Ferreira, Joao Marcelo [1 ]
Pinheiro, Alan Cadore [1 ]
Webber, Thais [3 ]
Marcon, Cesar [3 ]
机构
[1] Univ Fed Ceara, LESC DETI, BR-90455970 Fortaleza, Ceara, Brazil
[2] Polytech Nice Sophia Antipolis, Dept Elect, F-06410 Biot, France
[3] Pontificia Univ Catolica Rio Grande do Sul, PPGCC, BR-90619900 Porto Alegre, RS, Brazil
来源
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) | 2015年
关键词
Fault-tolerance; NoC; latency evaluation;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Each new production technology of integrated circuit (IC) drives more transistors area reduction, implying smaller and denser circuits. This scenario allows integrating several Processing Elements (PEs) into the same IC with efficient communication architecture such as the scalable topologies of Network on Chip (NoC). However, these newer production technologies introduce more defects in various parts of the IC that have to be detected and well corrected to prevent malfunction of the IC. This work presents the Fault Prediction Module (FPM), which presents low area consumption and a power circuit based on thresholds enabling to detect link quality, i.e. operating properly, operating with fault tendency or with permanent fault. Additionally, we show how to tune the FPM threshold parameter aiming to use this circuit as a mechanism with comprehensive fault model. The set of experimental results shows the effectiveness of our proposal.
引用
收藏
页码:284 / 288
页数:5
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