Study of Stencil Printing Technology for Fine Pitch Flip Chip Bumping

As miniaturization is the permanent pursuit of microelectronic industry, stencil printing technology for flip chip bumping has been contributing to this trend for almost half a century. Nowadays, it's still one of the lowest cost solutions to massive manufacture of IC packaging industry. To meet the requirement of further miniaturization, this paper investigated the realization of fine pitch (about 100 mu m and sub 100 mu m) printing bumps on silicon wafers in-house. Electroformed stencil was fabricated and commercial printer was employed for bumping printing. Type-6 solder pastes (both leaded and lead-free), self-designed pallets, dummy wafers, etc., were applied in this report. This paper closely investigated the practicable industry application of the fine pitch printing technology, and showed an integrated process to acquire industry-feasible fine pitch bumps including stencil design, dummy wafer design, materials and equipment preparation, etc. The essential parameters for printing process are presented as well. Finally, the printing results showed that area arrays at pitches larger than 130 mu m and parallel arrays at pitches larger than 110 mu m were well achieved. Meanwhile, the problems on finer pitches' realization, aperture shapes, and solder wettability were brought on.