Power optimization in low-voltage high-speed high-resolution pipelined ADCs

被引：2

作者：

Sarbishaei, Hassan ^{[1
]}

Tabasy, Ehsan Zhian ^{[1
]}

Toosi, Tahereh Kahookar ^{[1
]}

Lotfi, Reza ^{[1
]}

机构：

[1] Ferdowsi Univ Mashhad, Dept Elect Engn, Integrated Syst Lab, Mashhad, Iran

来源：

IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II | 2006年

关键词：

D O I：

10.1109/MWSCAS.2006.382232

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low-power design of low-voltage high-speed high-resolution A/D converters is presented. By expressing the total current consumption of the ADC as well as the ADC noise power as functions of the stage resolutions, the stage capacitors and the compensation capacitors of the cascode-compensated opamps, all those parameters are optimally determined in order to minimize power consumption for a definite budget for the noise power. In this methodology, the small-signal settling is considered as well as the large-signal settling. Besides, the contribution of the comparators is considered in the entire ADC current consumption. At last two power-optimized pipelined ADCs utilizing the proposed and conventional design methods are presented and compared in 0.18 mu m CMOS technology with 1.2V supply voltage. Considerable reduction in power consumption is achieved.

引用

页码：153 / +

页数：2

共 16 条

[1] AN IMPROVED FREQUENCY COMPENSATION TECHNIQUE FOR CMOS OPERATIONAL-AMPLIFIERS [J].

AHUJA, BK .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (06) :629-633

[2] A power optimized 13-b Msamples/s pipelined analog-to-digital converter in 1.2 mu m CMOS [J].

Cline, DW ;

Gray, PR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (03) :294-303

[3] Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping [J].

Dessouky, M ;

Kaiser, A .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) :349-355

[4]

Feldman A., 1997, THESIS U CALIFORNIA

[5] Systematic design for optimization of high-speed self-calibrated pipelined A/D converters [J].

Goes, J ;

Vital, JC ;

Franca, JE .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1998, 45 (12) :1513-1526

[6]

HERSHENSON M, 2002, P IEEE INT C COMP AI

[7] OPTIMIZING THE STAGE RESOLUTION IN PIPELINED, MULTISTAGE, ANALOG-TO-DIGITAL CONVERTERS FOR VIDEO-RATE APPLICATIONS [J].

LEWIS, SH .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (08) :516-523

[8]

Lin Y, 2005, IEEE INT SYMP CIRC S, P1968

[9] Power consumption issues in high-speed high-resolution pipelined A/D converters [J].

Lotfi, R ;

Taherzadeh-Sani, M ;

Shoaei, O .

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, :4618-4621

[10]

Lotfi R, 2003, ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P334

← 1 2 →