A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

被引：1

作者：

Chen, Cheng ^{[1
]}

Yuan, Jiren ^{[1
]}

机构：

[1] Lund Univ, Dept Electrosci, CCCD, Lund, Sweden

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.377923

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A 10-bit two-step subranging folding analog-todigital converter (ADC) that converts signal at 500 Msample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250NMz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13 mu m CMOS process. The chip occupies an active area of 0.54mm(2).

引用

页码：1709 / 1712

页数：4

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