A 1.2V 8Gb 8-Channel 128GB/s High-Bandwidth Memory (HBM) Stacked DRAM with Effective Microbump I/O Test Methods Using 29nm Process and TSV

被引：0

作者：

Lee, Dong Uk ^{[1
]}

Kim, Kyung Whan ^{[1
]}

Kim, Kwan Weon ^{[1
]}

Kim, Hongjung ^{[1
]}

Kim, Ju Young ^{[1
]}

Park, Young Jun ^{[1
]}

Kim, Jae Hwan ^{[1
]}

Kim, Dae Suk ^{[1
]}

Park, Heat Bit ^{[1
]}

Shin, Jin Wook ^{[1
]}

Cho, Jang Hwan ^{[1
]}

Kwon, Ki Hun ^{[1
]}

Kim, Min Jeong ^{[1
]}

Lee, Jaejin ^{[1
]}

Park, Kun Woo ^{[1
]}

Chung, Byongtae ^{[1
]}

Hong, Sungjoo ^{[1
]}

机构：

[1] SK Hynix, Inchon, South Korea

来源：

2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) | 2014年 / 57卷

关键词：

D O I：

10.1109/isscc.2014.6757501

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：432 / +

页数：3

共 4 条

[1] A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
Lee, Dong Uk
Kim, Kyung Whan
Kim, Kwan Weon
Lee, Kang Seol
Byeon, Sang Jin
Kim, Jae Hwan
Cho, Jin Hee
Lee, Jaejin
Chun, Jun Hyun
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (01) : 191 - 203
[2] A 1.2V 64Gb 8-Channel 256GB/s HBM DRAM with Peripheral-Base-Die Architecture and Small-Swing Technique on Heavy Load Interface
Lee, Jong Chern
Kim, Jihwan
Kim, Kyung Whan
Ku, Young Jun
Kim, Dae Suk
Jeong, Chunseok
Yun, Tae Sik
Kim, Hongjung
Cho, Ho Sung
Kim, Yeon Ok
Kim, Jae Hwan
Kim, Jin Ho
Oh, Sangmuk
Lee, Hyun Sung
Kwon, Ki Hun
Lee, Dong Beom
Choi, Young Jae
Lee, Jeajin
Kim, Hyeon Gon
Chun, Jun Hyun
Oh, Jonghoon
Lee, Seok Hee
2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 318 - U443
[3] An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with Non-Contact Microbump I/O Test Scheme
Yoon, Young Jun
Jeon, Byung Deuk
Kim, Byung Soo
Kim, Ki Up
Lee, Tae Yong
Kwak, Nohhyup
Shin, Woo Yeol
Kim, Na Yeon
Hong, Yunseok
Kang, Kyeong Pil
Ka, Dong Yoon
Lee, Seong Ju
Kim, Yong Sun
Noh, Young Kyu
Kim, Jaehoon
Kang, Dong Keum
Song, Ho Uk
Kim, Hyeon Gon
Oh, Jonghoon
2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 320 - U446
[4] A 1.2V 20nm 307GB/s HBM DRAM with At-Speed Wafer-Level I/O Test Scheme and Adaptive Refresh Considering Temperature Distribution
Sohn, Kyomin
Yun, Won-Joo
Oh, Reum
Oh, Chi-Sung
Seo, Seong-Young
Park, Min-Sang
Shin, Dong-Hak
Jung, Won-Chang
Shin, Sang-Hoon
Ryu, Je-Min
Yu, Hye-Seung
Jung, Jae-Hun
Nam, Kyung-Woo
Choi, Seouk-Kyu
Lee, Jae-Wook
Kang, Uksong
Sohn, Young-Soo
Choi, Jung-Hwan
Kim, Chi-Wook
Jang, Seong-Jin
Jin, Gyo-Young
2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 316 - U440

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