Physical synthesis of quantum circuits using templates

被引:5
作者
Mirkhani, Zahra [1 ]
Mohammadzadeh, Naser [1 ]
机构
[1] Shahed Univ, Dept Comp Engn, Tehran, Iran
关键词
Quantum computing; Physical design; Physical synthesis; Template matching; ION-TRAP; FAULT-TOLERANT; DESIGN; ARCHITECTURE;
D O I
10.1007/s11128-016-1377-x
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of "physical synthesis" was introduced for quantum circuit flow, and a few techniques were proposed for it. Following that concept, in this paper a new approach for physical synthesis inspired by template matching idea in quantum logic synthesis is proposed to improve the latency of quantum circuits. Experiments show that by using template matching as a physical synthesis approach, the latency of quantum circuits can be improved by more than 23.55 % on average.
引用
收藏
页码:4117 / 4135
页数:19
相关论文
共 53 条
[1]   Exact Template Matching Using Boolean Satisfiability [J].
Abdessaied, Nabila ;
Soeken, Mathias ;
Wille, Robert ;
Drechsler, Rolf .
2013 IEEE 43RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2013), 2013, :328-333
[2]   Designing a Million-Qubit Quantum Computer Using a Resource Performance Simulator [J].
Ahsan, Muhammad ;
Van Meter, Rodney ;
Kim, Jungsang .
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2016, 12 (04)
[3]  
Ahsan M, 2015, DES AUT TEST EUROPE, P1108
[4]  
[Anonymous], 2005, APPROACHING QUANTUM
[5]  
[Anonymous], 2005, REVERSIBLE LOGIC SYN
[6]  
Arabzadeh Mona, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), P849, DOI 10.1109/ASPDAC.2010.5419684
[7]   An MINLP Model for Scheduling and Placement of Quantum Circuits with a Heuristic Solution Approach [J].
Bahreini, Tayebeh ;
Mohammadzadeh, Naser .
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2015, 12 (03)
[8]   QUALE: Quantum architecture layout evaluator [J].
Balensiefer, S ;
Kreger-Stickles, L ;
Oskin, M .
Quantum Information and Computation III, 2005, 5815 :103-114
[9]   An evaluation framework and instruction set architecture for ion-trap based quantum micro-architectures. [J].
Balensiefer, S ;
Kregor-Stickles, L ;
Oskin, M .
32ND INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 2005, :186-196
[10]   OPTIMIZATION USING SIMULATED ANNEALING [J].
BROOKS, SP ;
MORGAN, BJT .
STATISTICIAN, 1995, 44 (02) :241-257