Behavioral synthesis with SystemC

被引：9

作者：

Economakos, G ^{[1
]}

Oikonomakos, P ^{[1
]}

Panagopoulos, I ^{[1
]}

Poulakis, I ^{[1
]}

Papakonstantinou, G ^{[1
]}

机构：

[1] Natl Tech Univ Athens, Dept Elect & Comp Engn, GR-15773 Athens, Greece

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/DATE.2001.914995

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Having to cope with the continuously increasing complexity of modern digital sq stems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year, the introduction of a new language for hardware descriptions, the SystemC C++ class library. initiated a closer relationship between software and hardware descriptions and development tools. This paper presents a synthesis environment and the corresponding synthesis methodology based on traditional compiler generation techniques, which incorporate SystemC, VHDL and Verilog to transform existing algorithmic software models into hardware system implementations. Following this approach, reusability of software components is introduced in the hardware world and time-to-marker is decreased, as shown by experimental results.

引用

页码：21 / 25

页数：5

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