In-system silicon validation and debug

被引:45
作者
Abramovici, Miron [1 ]
机构
[1] DAFCA, Framingham, MA 01701 USA
来源
IEEE DESIGN & TEST OF COMPUTERS | 2008年 / 25卷 / 03期
关键词
Assertions; Logic analysis; On-chip instrumentation; Reconfigurable infrastructure; Silicon debug; Silicon validation; System validation;
D O I
10.1109/MDT.2008.77
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip's development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. Other difficulties include nondeterministic operation and lack of time-specific expected values. This article presents a new approach that provides an efficient scalable solution to overcome these difficulties. The end results are a significant reduction of the silicon validation and debug time, and faster discovery and root-cause determination of integration problems, design bugs, and chip defects. © 2008 IEEE.
引用
收藏
页码:216 / 223
页数:8
相关论文
共 7 条
[1]  
Abramovici M., 2007, US patent, Patent No. [7,296,201, 7296201]
[2]   A reconfigurable Design-for-Debug infrastructure for SoCs [J].
Abramovici, Miron ;
Bradley, Paul ;
Dwarakanath, Kumar ;
Levin, Peter ;
Memmi, Gerard ;
Miller, Dave .
43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, :7-+
[3]  
Boulé M, 2007, ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, P613
[4]  
Dahlgren P, 2003, INT TEST CONF P, P755, DOI 10.1109/TEST.2003.1270905
[5]  
REDDY VK, 2006, P 24 INT C COMP DES
[6]   Core-based scan architecture for silicon debug [J].
Vermeulen, B ;
Waayers, T ;
Goel, SK .
INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, :638-647
[7]  
VERMEULEN B, 2002, IEEE DES TEST COMPUT, V19, P35