Two-step Vcm-based MS switching method with dual-capacitive arrays for SAR ADCs

被引：8
作者：
Huang, Jun [1 ]
Wu, Jianhui [1 ]
Wu, Aidong [1 ]
机构：
[1] Southeast Univ, Natl ASIC Res Ctr, Nanjing 210096, Jiangsu, Peoples R China
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2018年 / 94卷 / 01期
基金：
中国国家自然科学基金;
关键词：
SAR ADC; Switching method; Two-step; V-cm-based; Linearity; Ultra-low-power; ENERGY-EFFICIENT; SCHEME;
D O I：
10.1007/s10470-017-1082-4
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An ultra-low-power two-step merge and split (MS) switching method for a dual-capacitive arrays (DCAs) successive approximation register analogue-to-digital converter is presented. This method only requires two reference levels, i.e. Gnd and V-cm (V-cm = 1/2V(ref)). Compared with the conventional method, the proposed method achieves 99.89 and 80.96% reduction in average switching energy and capacitors, respectively, meanwhile maintaining good linearity. In addition, it barely consumes reset energy and keeps common-mode voltage of DCAs almost constant.
引用
收藏
页码：155 / 160
页数：6
相关论文
共 11 条
[1]   High efficiency two-step capacitor switching scheme for SAR ADC [J].
Ding, Zhen ;
Zhu, Zhangming .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 86 (01) :127-131
[2]   Trade-off between energy and linearity switching scheme for SAR ADC [J].
Ding, Zhen ;
Bai, Wenbin ;
Zhu, Zhangming .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 86 (01) :121-125
[3]   Energy-efficient charge-recovery switching scheme for dual-capacitive arrays SAR ADC [J].
Li, Y. ;
Zhang, Z. ;
Lian, Y. .
ELECTRONICS LETTERS, 2013, 49 (05) :330-331
[4]   A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS [J].
Lin, Jin-Yi ;
Hsieh, Chih-Cheng .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (01) :70-79
[5]   Two-step reset method for energy-efficient SAR ADC switching schemes [J].
Osipov, D. ;
Paul, St. .
ELECTRONICS LETTERS, 2016, 52 (10) :816-817
[6]   Two advanced energy-back SAR ADC architectures with 99.21 and 99.37 % reduction in switching energy [J].
Osipov, Dmitry ;
Paul, Steffen .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 87 (01) :81-91
[7]   Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC [J].
Wang, Hao ;
Zhu, Zhangming ;
Ding, Ruixue .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2015, 85 (02) :373-377
[8]   Energy-efficient switching scheme for ultra-low voltage SAR ADC [J].
Wu, Aidong ;
Wu, Jianhui ;
Huang, Jun .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 90 (02) :507-511
[9]   Low-power bottom-plate sampling capacitor-splitting DAC for SAR ADCs [J].
Yazdani, B. ;
Khorami, A. ;
Sharifkhani, M. .
ELECTRONICS LETTERS, 2016, 52 (11) :913-914
[10]   Low-energy and area-efficient tri-level switching scheme for SAR ADC [J].
Yuan, C. ;
Lam, Y. .
ELECTRONICS LETTERS, 2012, 48 (09) :482-U30
12