Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators

被引:2
作者
Chakraborty, Abhishek [1 ]
Srivastava, Ankur [1 ]
机构
[1] Univ Maryland, Dept Elect & Comp Engn, College Pk, MD 20742 USA
来源
2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019) | 2019年
关键词
D O I
10.1109/ISVLSI.2019.00104
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Existing logic obfuscation approaches aim to protect hardware design IPs from SAT attack by increasing query count and output corruptibility of a locked netlist. In this paper, we demonstrate the ineffectiveness of such techniques to obfuscate hardware accelerator platforms. Subsequently, we propose a Hardware/software co-design based Accelerator Obfuscation (HSCAO) scheme to provably safeguard the IP of such designs against SAT as well as removal/bypass type of attacks while still maintaining high output corruptability for applications. The attack resiliency of HSCAO scheme is manifested by using a sequence of keys to obfuscate instruction encoding for an application. Experimental evaluations utilizing an accelerator simulator demonstrate the effectiveness of our proposed countermeasure.
引用
收藏
页码:549 / 554
页数:6
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