Fast configurable-cache tuning with a unified second-level cache

被引：21

作者：

Gordon-Ross, A ^{[1
]}

Vahid, F ^{[1
]}

Dutt, N ^{[1
]}

机构：

[1] Univ Calif Riverside, Dept Comp Sci & Engn, Riverside, CA 92521 USA

来源：

ISLPED '05: Proceedings of the 2005 International Symposium on Low Power Electronics and Design | 2005年

关键词：

configurable cache; cache hierarchy; cache exploration; cache optimization; low power; low energy; architecture tuning; embedded systems;

D O I：

10.1109/LPE.2005.195540

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or a second level with separate instruction and data configurable caches. We instead use a commercially-common unified second level, a seemingly minor difference that actually expands the configuration space from 500 to about 20,000. We develop additive way tuning for tuning a cache subsystem with this large space, yielding 62% energy savings and 35% performance improvements over a non-configurable cache, greatly outperforming an extension of a previous method.

引用

页码：323 / 326

页数：4