Circuit design and modeling for soft errors

被引：15

作者：

Kleinsowski, A. J. ^{[1
]}

Cannon, Ethan H. ^{[2
]}

Oldiges, Phil ^{[3
]}

Wissel, Larry ^{[2
]}

机构：

[1] IBM Austin Res Lab, Div Res, Austin, TX 78758 USA

[2] IBM Syst & Technol Grp, Essex Jct, VT 05452 USA

[3] IBM Corp, Semicond Res & Dev Ctr, Syst & Technol Grp, Hopewell Jct, NY 12533 USA

来源：

IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2008年 / 52卷 / 03期

关键词：

D O I：

10.1147/rd.523.0255

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error rates with reasonable accuracy. As the technology matures, circuit test sites are produced and experimentally tested to determine representative fail rates of critical SRAM and flip-flop circuits. Circuit models are then fit to these experimental results and further test-site and product circuits are designed and modeled as needed.

引用

页码：255 / 263

页数：9

共 27 条

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Baumann R. C., 2001, IEEE Transactions on Device and Materials Reliability, V1, P17, DOI 10.1109/7298.946456

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