Priority Encoder using reversible logic gates in QCA

被引：0

作者：

Sen, Riya ^{[1
]}

Das, Sandip ^{[1
]}

Mazumder, Gitika Guha ^{[1
]}

Yadav, Priyanka ^{[1
]}

Neogy, Ballary ^{[1
]}

Pandey, Rohit ^{[1
]}

Sharma, Shalu ^{[1
]}

Jana, Biswajit ^{[1
]}

机构：

[1] Univ Engn & Management, Elect & Commun Engn, Jaipur, Rajasthan, India

来源：

2017 8TH IEEE ANNUAL INFORMATION TECHNOLOGY, ELECTRONICS AND MOBILE COMMUNICATION CONFERENCE (IEMCON) | 2017年

关键词：

Reversible logic; Fredkin gate; URLG; QCA; priority encoder; DESIGN;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Reversible logic gate has gained importance in recent times due to its low power dissipation and less information loss. QCA on the other hand has low power consumption and has applications in reversible logic. In this paper, a 4x2 priority encoder is proposed which is based on reversible logic implemented in QCA. Firstly, this paper discusses about QCA layout design of Fredkin gate and Universal Reversible Logic Gate (URLG). Secondly, this paper uses reversible logic gate (both Fredkin and URLG) to design a 4x2 priority encoder in QCA.

引用

页码：319 / 323

页数：5

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