An Ultra-fast ADC Linearity Test and Calibration Method

An ultra-fast and low-cost testing and calibration method for successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The ADC nonlinearities are modeled as segmented parameters with inter-segment mismatch errors. During the test phase, a pure signal with known feature such as a pure sine wave is sent as input and the model parameters are estimated from the output data with the proposed method. Significantly, much fewer samples are required when compared to traditional histogram testing. During the calibration phase, the modeled errors are then removed from the digital output codes. With just 4000 samples, a 16-bit ADC can be accurately tested and calibrated to achieve less than 0.4 least significant bit (LSB) integral nonlinearity (INL). The measurement results show that, ADC effective number of bits (ENOB) is improved from 13.3 to 15.6 bits and the spurious-free dynamic range (SFDR) is improved from 86dB to 118dB (boost 32 dB) after calibration. The proposed method can be applied to all kinds of A/D Converters.