A 4MS/s 10b SAR ADC with integrated C ass-A buffers in 65nm CMOS with near rail-torail input using a single 1.2V supply

We present a 1013 differential SAR ADC integrated with unity gain (Class-A) voltage buffers, operating from a single supply voltage 1.2V and handling near raibto- rail inputs. The two differential inputs are first compared and depending on the comparison result, the inputs are either swapped or not, after which these signals are buffered, sampled and converted. This way each of the two buffers needs to handle only half of the full-scale range which enables operation of the Class -A buffers at the ADC supply voltage while providing an overall near rail -to-rail (fullscale) input range for conversion. The buffered ADC can handle y_p differential input and consumes 149itW at,IALSts to achieve a state-of-the-art Walden FoM of 870/conversion-step including buffers. The buffered ADC was designed in a 65nm CMOS process and occupies an actis e area of 0.04m m2,