Efficient Column-Layered Decoders for Single Block-Row Quasi-Cyclic LDPC Codes

被引：0

作者：

Zhang, Chuan ^{[1
]}

You, Xiaohu ^{[1
]}

Wang, Zhongfeng ^{[2
]}

机构：

[1] Southeast Univ, Sch Informat Sci & Engn, Natl Mobile Commun Res Lab, Nanjing, Jiangsu, Peoples R China

[2] Broadcom Corp, Irvine, CA 92617 USA

来源：

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2014年

基金：

对外科技合作项目（国际科技项目）;

关键词：

Low-density parity-check (LDPC) codes; single block-row; column-layered; single-minimum; PARITY-CHECK CODES;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.

引用

页码：413 / 416

页数：4

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