Efficient framework for accelerating functional verification of microprocessor

This paper presents a simulation-based function verification framework featured by two efficient acceleration techniques, namely -'self-verifying" and of mixed models". The former automates the verification process over the whole vector space by eliminating manual interference, the effect of which is directly proportional to the size of vector space and average vector size. The latter reduces the time required to simulate full-chip netlist from exponential to linear relationship with the number of modules by co-simulating the mixed models of RFL and netlist. Benefit of this framework was well exhibited in the verification practice of a 32-bit high-end processor. The prototype processor fabricated on 0. 18um CMOS process technology functioned properly under system environment test, which indicated the framework presented feasible.