At-speed test for path delay faults using practical techniques

被引：1

作者：

Qiu, WQ ^{[1
]}

Wang, J ^{[1
]}

Lu, X ^{[1
]}

Li, Z ^{[1
]}

Walker, DMH ^{[1
]}

Shi, WP ^{[1
]}

机构：

[1] Texas A&M Univ, Dept Comp Sci, College Stn, TX 77843 USA

来源：

DBT 2004: PROCEEDINGS OF THE 2004 IEEE INTERNATIONAL WORKSHOP ON CURRENT & DEFECT BASED TESTING | 2004年

关键词：

D O I：

10.1109/DBT.2004.1408957

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Most existing test generation tools are either inefficient in automatically identifying the longest testable paths due to the high computational complexity or do not support at-speed test using existing practical design-for-testability structures, such as scan design. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on the ISCAS89 benchmark circuits.

引用

页码：61 / 66

页数：6

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