Speech Recognition System and its Automatic Synthesis in Hardware

被引：0

作者：

Buitrago, J. ^{[1
]}

Aedo, J. ^{[1
,3
]}

Rivera, F. ^{[2
,3
]}

机构：

[1] Univ Antioquia, Elect Engn Dept, Antioquia, Colombia

[2] Univ Antioquia, Comp Sci Dept, Antioquia, Colombia

[3] ARTICA, Helsinki, Finland

来源：

2010 IEEE ELECTRONICS, ROBOTICS AND AUTOMOTIVE MECHANICS CONFERENCE (CERMA 2010) | 2010年

关键词：

D O I：

10.1109/CERMA.2010.131

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper a methodology to perform optimizations in the hardware implementation of a speech recognizer is presented; this methodology explores the design space from a very high level representation of the algorithm. We expose how to accelerate the process of speech recognition by exploiting the inherently concurrent decoding stage. Finally, we show the cost in terms of hardware resources required to synthesize the speech recognition algorithms.

引用

页码：672 / 676

页数：5

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