Design of 1024-I/Os 3.84 GB/s high bandwidth 600 mW low power 16 Mb DRAM macros for parallel image processing RAM

被引：0

作者：

Aimoto, Y ^{[1
]}

Kimura, T

Yabe, Y

Heiuchi, H

Nakazawa, Y

Motomura, M

Koga, T

Fujita, Y

Hamada, M

Tanigawa, T

Nobusawa, H

Koyama, K

机构：

[1] NEC Corp Ltd, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291134, Japan

[2] NEC Corp Ltd, Incubat Ctr, Kanagawa 2160034, Japan

[3] NEC Corp Ltd, ULSI Device Dev Labs, Sagamihara, Kanagawa 2291134, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 1998年 / E81C卷 / 05期

关键词：

integration of DRAM and logic; embedded DRAM; low power; high memory bandwidth;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0.38-mu m CMOS 64-Mb DRAM process technology. It achieves 7.68-GIPS processing performance and 3.84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz),and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.

引用

页码：759 / 767

页数：9