A 3-Bit Flash Spin-Orbit Torque (SOT)-Analog-to-Digital Converter (ADC)

被引:6
作者
Ghanatian, Hamdam [1 ]
Farkhani, Hooman [1 ]
Rezaeiyan, Yasser [1 ]
Bohnert, Tim [2 ]
Ferreira, Ricardo [2 ]
Moradi, Farshad [1 ]
机构
[1] Aarhus Univ, Dept Elect & Comp Engn, Integrated Circuits & Elect Lab ICE LAB, DK-8200 Aarhus, Denmark
[2] Int Iberian Nanotechnol Lab INL, P-4715330 Braga, Portugal
关键词
Flash analog-to-digital converter (ADC); magnetic tunnel junction (MTJ); spin-orbit torque (SOT); spin-transfer torque (STT); MAGNETIC TUNNEL-JUNCTION; SPINTRONICS;
D O I
10.1109/TED.2022.3142649
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this article, a 3-bit Flash spin-orbit torque analog-to-digital converter (SOT-ADC) is presented, which works based on switching of a perpendicular-anisotropy magnetic tunnel junction (p-MTJ) by the spin Hall effect (SHE) assisted by spin-transfer torque (STT). To quantize the input signal into eight states, a heavymetal (HM) with different cross-sectional areas that are shared with seven magnetic tunnel junctions (MTJs) is utilized. To enable the deterministic switching, STT currents are employed. However, such currentsmake challenges during conversion and sensing phases, which are addressed in thiswork. The SOT-ADC eliminates the (2(n) - 1)-time duplication of the input current (I-in) in conventionaln- bit current-mode complementary metal-oxide-semiconductor (CMOS) Flash analog-to-digital converters (ADCs). Each MTJ acts as a comparator that compares the input signal (current) with its own critical current (I-C) as a reference current (I-ref). Therefore, the power-hungry comparators in CMOS Flash ADCs can be replaced by simple latch-based comparators for sensing the states of MTJs. Moreover, instead of using different sizes of transistors to create various values of I-ref, i.e., I-ref1, 2I(ref1), . . ., fixed currents as sensing currents are used, which leads to reducing mismatch issue and chip area. Because of the influence of the resistance of HM, each MTJ has an exclusive reference voltage (V-ref) that is created by a dummy 3-bit spin-orbit torque (SOT)-quantizer. According to the simulation results, power consumption and maximum sampling rate (including all conversion, sensing, and reset phases) of the ADC are 416 mu W and 102 MS/s in 180-nm CMOS technology, respectively. In addition, the differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.258 and -0.275 least significant bit (LSB), respectively.
引用
收藏
页码:1691 / 1697
页数:7
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