Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops

被引:25
作者
Phyu, Myint Wai [1 ]
Fu, Kangkang [1 ]
Goh, Wang Ling
Yeo, Kiat-Seng
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, CICS, Singapore 639798, Singapore
关键词
Clock-gated; high-performance; low-power; sense-amplifier flip-flop; HIGH-PERFORMANCE;
D O I
10.1109/TVLSI.2009.2029116
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.
引用
收藏
页码:1 / 9
页数:9
相关论文
共 15 条
[1]  
Chien-Cheng Y, 2007, C IND ELECT APPL, P2054
[2]  
Ghadiri A, 2005, I CONF VLSI DESIGN, P846
[3]  
Gray P.R., 2000, ANAL DESIGN ANALOG I, V4th
[4]   A reduced clock-swing flip-flop (RCSFF) for 63% power reduction [J].
Kawaguchi, H ;
Sakurai, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (05) :807-811
[5]   Presetting pulse-based flip-flop [J].
Kim, Chul-Soo ;
Kim, Joo-Seong ;
Kong, Bai-Sun ;
Moon, Yongsam ;
Jun, Young-Hyun .
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, :588-+
[6]   Dual edge-triggered flip-flop with modified NAND keeper for high-performance VLSI [J].
Kim, JI ;
Kong, BS .
CURRENT APPLIED PHYSICS, 2004, 4 (01) :49-53
[7]   Conditional-capture flip-flop for statistical power reduction [J].
Kong, BS ;
Kim, SS ;
Jun, YH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (08) :1263-1271
[8]  
Liu YT, 2006, IEEE INT SYMP CIRC S, P4329
[9]  
Nedovic N, 2002, ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P56, DOI 10.1109/LPE.2002.1029540
[10]   Improved sense-amplifier-based flip-flop: Design and measurements [J].
Nikolic, B ;
Oklobdzija, VG ;
Stojanovic, V ;
Jia, WY ;
Chiu, JKS ;
Leung, MMT .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (06) :876-884