Back gate bias effect and layout dependence on Random Telegraph Noise in FDSOI technologies

被引：1
|
作者：
Srinivasan, P. [1 ]
Song, D. [1 ]
Rose, D. [1 ]
LaCroix, M. [1 ]
Dasgupta, A. [1 ]
机构：
[1] GLOBALFOUNDRIES Inc, Stonebreak Rd Extens, Malta, NY 12020 USA
来源：
2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2021年
关键词：
RTN; FDSOI; back gate; FinFET; layout; SIGNAL;
D O I：
10.1109/IRPS46558.2021.9405199
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
The effect of back gate bias and device layout design on Random Telegraph Noise (RTN) behavior is discussed. The effect of RTN on multi-PC fingers fully-depleted Silicon on Insulator (FDSOI) devices were studied in both front gate (FG) and front gate connected to back-gate (FG + BG) condition. Lower RTN induced gate voltage a, variation is noticed in FG+BG condition than FG. In addition, higher amplitude variation occurs in single-PC devices. Similar level of RTN induced gate voltage variation mean is observed in comparison with bulk FinFET, although the distributions are different.
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页数：4
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