Optimization of silicon epitaxial wafers for microcontamination and particle performance

被引：0

作者：

Waldhauer, A ^{[1
]}

Comita, PB ^{[1
]}

Thilderkvist, A ^{[1
]}

Tuncel, E ^{[1
]}

Carlson, D ^{[1
]}

机构：

[1] Appl Mat Inc, Epi Div, Silicon Epitaxy Dev Lab, Santa Clara, CA 95054 USA

来源：

HIGH PURITY SILICON V | 1998年 / 98卷 / 13期

关键词：

D O I：

暂无

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The use of epitaxial wafers for VLSI device processing offers numerous advantages over polished wafers. These include latch-up control for heavily doped substrates and reduced defects in the near surface region. The crystal originated particle defects (COPs) can be reduced by using a silicon epitaxy layer, resulting in increased device yields. Optimization of the epitaxy process is described for reduction of light point defects, metal contamination, and 300mm wafer sizes.

引用

页码：90 / 97

页数：8