Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval

被引：4

作者：

Chikhi, Rayan ^{[2
]}

Derrien, Steven ^{[1
]}

Noumsi, Auguste ^{[3
]}

Quinton, Patrice ^{[2
]}

机构：

[1] Univ Rennes & IRISA, F-35042 Rennes, France

[2] Ecole Normale Super Cachan & IRISA, F-35170 Bruz, France

[3] Univ Douala, Cameroun, France

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 2008年 / 95卷 / 07期

关键词：

high performance computing; image processing; reconfigurable architecture;

D O I：

10.1080/00207210801923679

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With ever larger and more affordable storage capabilities, individuals and companies can now collect huge amounts of multimedia data, especially images. Searching such databases is still an open problem, known as content-based image retrieval (CBIR). In this paper, we present a hardware architecture based on FPGAs which aims at speeding-up visual CBIR. Our architecture is based on the unique combination of reconfigurable resources and flash memory, allows for a speed-up factor of 45 as compared to existing software solutions.

引用

页码：621 / 635

页数：15

共 21 条

[1] Content-based retrieval using local descriptors: Problems and issues from a database perspective [J].