Strategies for Single Patterning of Contacts for 32nm and 28nm Technology

被引:0
作者
Morgenfeld, Bradley [1 ]
Stobert, Ian [1 ]
Haffner, Henning [4 ]
An, Ju J. [1 ]
Kanai, Hideki [2 ]
Ostermayr, Martin [4 ]
Chen, Norman [3 ]
Aminpur, Massud [1 ]
Brodsky, Colin [1 ]
Thomas, Alan [1 ]
机构
[1] IBM Semicond Res & Dev Ctr, 2070 Route 52, Hopewell Jct, NY 12533 USA
[2] Toshiba Amer Elect Components Inc, Hopewell Jct, NY 12533 USA
[3] GLOBALFOUNDRIES INC, Hopewell Jct, NY 12533 USA
[4] Infineon Technol NA Corp, Hopewell Jct, NY 12533 USA
来源
2011 22ND ANNUAL IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC) | 2011年
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device based performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally novel design changes for single patterning along new capability in data preparation were both assessed to leverage minimal impact of implementation of a single patterning contact process into the existing 32nm and 28nm technology programs [1].
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页数:8
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