An analytical model for a gate-induced-drain-leakage current in a buried-channel PMOSFET

被引：4

作者：

Kim, SH ^{[1
]}

Kim, SE ^{[1
]}

Park, JH ^{[1
]}

Kim, SH ^{[1
]}

Kim, MS ^{[1
]}

Koo, JM ^{[1
]}

Kim, BS ^{[1
]}

Kim, ES ^{[1
]}

Lee, SC ^{[1
]}

Choi, CS ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, LSI Proc Architecture, LSI Dev Team, Syst LSI Div, Yongin 449711, South Korea

来源：

JOURNAL OF THE KOREAN PHYSICAL SOCIETY | 2003年 / 43卷 / 05期

关键词：

MOSFET; GIDL; PMOS;

D O I：

10.3938/jkps.43.863

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

The gate-induced-drain-leakage (GIDL) current is generally known to originate from the difference between the vertical electric fields at the gate and the drain. When an 1-dimensional model simulation was carried out to analyze this phenomenon, a significant difference was found to exist between the 1-dimensional model simulation and the measured GIDL current. In this study, the subthreshold leak-age characteristics of a 0.25-mum-design ruled p-type metal-oxide-semiconductor-field emission-transistor (MOSFET) were analyzed using simulation modeling with a substrate-biased condition. The results of the fitting revealed that the subthreshold leakage was influenced by the vertical an electrical field between the gate and the drain, as well as by the lateral electrical field between the gate and the substrate. From this result, we could calculate the effect of the effective tunneling-barrier lowering on the band-trap-band tunneling GIDL phenomenon due to the lateral electric field, and we confirm that the measured result was well fitted by the calculation. Also, in order to clarify the effect of the lateral field, we monitored the trends of the GIDL current for different spacer lengths.

引用

页码：863 / 867

页数：5

共 8 条

[1] MECHANISMS OF INTERFACE TRAP-INDUCED DRAIN LEAKAGE CURRENT IN OFF-STATE N-MOSFETS [J].