A pipelined low power architectural MPEG-4 video codec chip with deblocking filter for mobile wireless multimedia applications

被引：2

作者：

Koo, B ^{[1
]}

Kim, S ^{[1
]}

Lee, S ^{[1
]}

Choi, M ^{[1
]}

Park, K ^{[1
]}

Eum, N ^{[1
]}

Kim, J ^{[1
]}

Cho, H ^{[1
]}

机构：

[1] ETRI, Adv Micro Elect Res Lab, Taejon, South Korea

来源：

2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ICASIC.2003.1277364

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in mobile wireless Multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance and low power consumption video compression/decompression chip. By introducing partitioning of HW/SW modules, the efficiently optimized frame memory interface architecture, motion estimation skip scheme, and macroblock based pipeline deblocking filtering scheme, the proposed MPEG-4 video codec has low power consumption for mobile wireless multimedia applications such as mobile phone, PDA and DMB. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz with 128ksimilar to144kbps rates. Power consumption is 290mW and the chip size is 9.7mm x 9.7mm at 0.35mum CMOS technology.

引用

页码：934 / 937

页数：4