Dynamic fault diagnosis of combinational and sequential circuits on reconfigurable hardware

被引:5
作者
Kocan, Fatih [1 ]
Saab, Daniel G.
机构
[1] So Methodist Univ, Dallas, TX 75275 USA
[2] Case Western Reserve Univ, Cleveland, OH 44106 USA
来源
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2007年 / 23卷 / 05期
关键词
dynamic fault diagnosis; stuck-at faults; circuits; gate-level; emulation; FPGA;
D O I
10.1007/s10836-007-5009-3
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the circuit under diagnosis (CUD). This method allows designers to perform dynamic fault location of stuck-at faults in large circuits, and eliminates the need for large storage required by a software-based fault dictionary. In fact, the approach is a pure hardware solution to fault diagnosis. We demonstrate the feasibility of the method in terms of hardware resources and diagnosis time by experimenting with ISCAS85 and ISCAS89 circuits. The emulation-based diagnosis method speeds up the diagnosis process by an order of magnitude compared to the software-based fault diagnosis. This speed-up is important, especially, when the on-line diagnosis of safety-critical systems is of concern.
引用
收藏
页码:405 / 420
页数:16
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