High performance processor array for image processing

被引：6

作者：

Foldesy, Peter ^{[1
]}

Zarandy, Akos ^{[1
]}

Rekeczky, Csaba ^{[1
]}

Roska, Tamas ^{[1
]}

机构：

[1] Hungarian Acad Sci, Comp & Automat Res Inst, Anal & Neural Comp Lab, Budapest, Hungary

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.378260

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The ASIC implementation of a digital Cellular Visual Microprocessor architecture is introduced. The processor array is constructed of simple, locally interconnected 8 bit microprocessors, operating in an extended SIMD mode. The processor array can be equipped with on-chip photo diode array, using 3D integration technology.

引用

页码：1177 / 1180

页数：4

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