Electrical Validation of Through Process OPC Verification Limits

被引：0

作者：

Jaiswal, Omprakash ^{[1
]}

Kuncha, Rakesh ^{[1
]}

Bharat, Taksh ^{[1
]}

Madangarli, Vipin ^{[1
]}

Conrad, Edward ^{[2
]}

Bruce, James ^{[2
]}

Marokkey, Sajan ^{[3
]}

机构：

[1] IBM India Pvt Ltd, Syst & Technol Grp, Bangalore 560045, Karnataka, India

[2] IBM Syst & Technol Grp, Essex Jct, VT 05452 USA

[3] Infineon Technol AG, Hopewell Jct, NY 12533 USA

来源：

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXIV | 2010年 / 7638卷

关键词：

OPC; Verification; Simulation; Process Window; Yield;

D O I：

10.1117/12.846572

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper. Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.

引用

页数：8

共 4 条

[1] Model-based verification for first time right manufacturing [J].

Bruce, JA ;

Conrad, EW ;

Dick, GJ ;

Nickel, DJ ;

Smolinski, JG .

Design and Process Integration for Microelectronic Manufacturing III, 2005, 5756 :198-207

[2] Predicting yield using model based OPC verification - Calibrated with electrical test data [J].

Bruce, James A. ;

Ting, Tso-Hui .

DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION II, 2008, 6925

[3] Dense OPC and verification for 45nm [J].

Cobb, Nicolas ;

Dudau, Dragos .

OPTICAL MICROLITHOGRAPHY XIX, PTS 1-3, 2006, 6154 :U291-U296

[4]

Karthikeyan M, 2006, ICMTS 2006: PROCEEDINGS OF THE 2006 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, P104

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