Isolation charge pump fabricated in silicon on sapphire CMOS technology

被引：7

作者：

Culurciello, E ^{[1
]}

Pouliquen, PO

Andreou, AG

机构：

[1] Yale Univ, Dept Elect Engn, New Haven, CT 06520 USA

[2] Johns Hopkins Univ, Dept Elect & Comp Engn, Baltimore, MD 21218 USA

来源：

ELECTRONICS LETTERS | 2005年 / 41卷 / 10期

关键词：

D O I：

10.1049/el:20050312

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design, fiabrication and testing of a four-stage charge-pump fabricated in a 0.5 mu m silicon-on-sapphire CMOS technology is reported. The charge pump can generate a 2.68 V output with a 3.3 V input power supply, consuming 2.5 mA. The performance of the architecture is optimised by judiciously employing MOS transistors with different threshold (0, 0.3 and 0.7 V) in the different parts of the circuit. The charge pump input and output power supplies are galvanically isolated to over 800 V by means of the dielectric properties of the coupling capacitors and the insulating sapphire substrate.

引用

页码：590 / 592

页数：3

共 6 条

[1]

Andreou A. G., 2001, IEEE Circuits and Systems Magazine, V1, P22, DOI 10.1109/7384.963464

[2]

CHENG K, 2003, IEEE INT S CIRC SYST, V5, pV89

[3] ON-CHIP HIGH-VOLTAGE GENERATION IN MNOS INTEGRATED-CIRCUITS USING AN IMPROVED VOLTAGE MULTIPLIER TECHNIQUE [J].