Efficient interpolation and factorization in algebraic soft-decision decoding of Reed-Solomon codes

被引：0
|
作者：
Koetter, R [1 ]
Ma, J [1 ]
Vardy, A [1 ]
Ahmed, A [1 ]
机构：
[1] Univ Illinois, Coordinated Sci Lab, Urbana, IL 61801 USA
来源：
2003 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY - PROCEEDINGS | 2003年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The main computational steps in algebraic soft-decoding of Reed-Solomon codes are bivariate interpolation and factorization. We discuss a new computational technique, based upon re-encoding and coordinate transformation, that significantly reduces the complexity of interpolation and factorization. The re-encoding procedure and the coordinate transformation convert the original interpolation problem into another reduced interpolation problem, which is orders of magnitude smaller than the original one.
引用
收藏
页码：365 / 365
页数：1
相关论文
共 50 条
  • [21] Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes
    Zhu, Jiangli
    Zhang, Xinmiao
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (10) : 3050 - 3062
  • [22] FPGA implementation of an interpolation processor for soft-decision decoding of reed-solomon codes
    School of EECS, Oregon Sate University, Corvallis, OR 97331-3211, United States
    不详
    Proc IEEE Int Symp Circuits Syst, 2007, (2100-2103):
  • [23] A VLSI architecture for interpolation in soft-decision list decoding of Reed-Solomon codes
    Gross, WJ
    Kschischang, FR
    Koetter, R
    Gulak, RG
    2002 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, 2002, : 39 - 44
  • [24] Exponential error bounds for algebraic soft-decision decoding of Reed-Solomon codes
    Ratnakar, N
    Koetter, R
    IEEE TRANSACTIONS ON INFORMATION THEORY, 2005, 51 (11) : 3899 - 3917
  • [25] Fast factorization architecture in soft-decision Reed-Solomon decoding
    Zhang, XM
    Parhi, KK
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (04) : 413 - 426
  • [26] Fast factorization architecture in soft-decision Reed-Solomon decoding
    Zhang, XM
    Parhi, KK
    2004 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, PROCEEDINGS, 2004, : 101 - 106
  • [27] AN EFFICIENT SOFT-DECISION REED-SOLOMON DECODING ALGORITHM
    TAIPALE, DJ
    SEO, MJ
    IEEE TRANSACTIONS ON INFORMATION THEORY, 1994, 40 (04) : 1130 - 1139
  • [28] Scalable Interpolation Architecture for Soft-decision Reed-Solomon Decoding
    Zhu, Jiangli
    Zhang, Xinmiao
    2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 41 - 44
  • [29] An FPGA interpolation processor for soft-decision reed-solomon decoding
    Gross, WJ
    Kschischang, FR
    Gulak, PG
    12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2004, : 310 - 311
  • [30] VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes
    Ahmed, Arshad
    Koetter, Ralf
    Shanbhag, Naresh R.
    IEEE TRANSACTIONS ON INFORMATION THEORY, 2011, 57 (02) : 648 - 667
12345