A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS

被引：10
作者：
Hung, Yu-Cherng [1 ]
Shieh, Shao-Hui [1 ]
Tung, Chiou-Kou [1 ]
机构：
[1] Natl Chin Yi Univ Technol, Dept Elect Engn, Taichung Cty 411, Taiwan
来源：
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2011年 / 20卷 / 01期
关键词：
Low voltage; low power; LVLP; BACK-GATE; PERFORMANCE; LEAKAGE; DESIGN; SCHEME; OPTIMIZATION; COMPARATOR; REDUCTION; ALGORITHM;
D O I：
10.1142/S0218126611007104
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.
引用
收藏
页码：89 / 105
页数：17
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