A system-on-chip dynamically reconfigurable FPGA platform for matrix inversion

被引：0

作者：

Jianwen, Luo ^{[1
]}

Chuen, Jong Ching ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Integrated Syst Res Lab, Singapore 639798, Singapore

来源：

2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2 | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Dynamically and partially reconfigurable (DPR) FPGA computing platform offers flexibility on both the parallel computation as well as hardware reconfiguration at run-time Self-reconfiguration which allows the FPGA resource to be reconfigured partially by the on chip configuration controller offers even greater configuration bandwidth. We design and put together a set of functional modules and compose a FPGA-based system-on-chip (SoC) DPR platform for hardware acceleration. Matrix inversion is used as an example to illustrate the design and operation of such a reconfiguration system. The proposed platform consists of a configurable module, in this case, a scalable CORDIC based QR factorization core designed for matrix inversion and a fixed module to support the dynamic partial reconfiguration. This paper describes the architecture and the components of the proposed DPR platform.

引用

页码：465 / 468

页数：4

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