共 50 条
[21]
A Combined Decimal and Binary Floating-point Multiplier
[J].
2009 20TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS,
2009,
:8-+
[22]
Implementation of Fused Floating Point Three Term Adder Unit
[J].
2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), VOL. 1,
2016,
:1343-1346
[23]
Dual-mode floating-point adder architectures
[J].
JOURNAL OF SYSTEMS ARCHITECTURE,
2008, 54 (12)
:1129-1142
[24]
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder
[J].
2023 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS,
2024,
:343-347
[26]
Reduced latency IEEE floating-point standard adder architectures
[J].
14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS,
1999,
:35-42
[27]
Design and Implementation for Quadruple Precision Floating-point Multiplier Based on FPGA with Lower Resource Occupancy
[J].
2014 Fifth International Conference on Intelligent Systems Design and Engineering Applications (ISDEA),
2014,
:326-329
[28]
FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier
[J].
2009 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS,
2009,
:6-11
[29]
Hardware Implementation of a High Speed Floating Point Multiplier Based on FPGA
[J].
ICCSSE 2009: PROCEEDINGS OF 2009 4TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION,
2009,
:1902-+